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addressing the slave, the host outputs the rest of the message with the 9 bit set to 0, so no additional
71M6543F/71M6543G Data Sheet
th
serial port receive interrupts is generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in Table 18 and Table 19, respectively, and the PCON register shown in Table 20 .
Since the TI0 , RI0 , TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided . The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except
for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to
ignore ones written to them.
Table 18: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
0
Description
N/A
SM0
0
SM1
0
S0CON[6]
SM1
1
2
3
8-bit UART
9-bit UART
9-bit UART
0
1
1
1
0
1
In Modes 2 and 3 it is the 9 data bit received. In Mode 1, SM20 is 0, RB80 is the
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
SM20
REN0
TB80
RB80
TI0
RI0
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
th
stop bit. In mode 0, this bit is not used. Must be cleared by software.
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
Table 19: The S1CON (UART1) Register (SFR 0x9B)
Bit
S1CON[7]
SM
Symbol
Function
Sets the baud rate and mode for UART1.
SM
0
1
Mode
A
B
Description
9-bit UART
8-bit UART
Baud Rate
variable
variable
The 9 transmitted data bit in Mode A. Set or cleared by the MPU, depending
In Modes A and B, it is the 9 data bit received. In Mode B, if SM21 is 0, RB81 is
S1CON[5]
S1CON[4]
S1CON[3]
S1CON[2]
S1CON[1]
S1CON[0]
v2
SM21
REN1
TB81
RB81
TI1
RI1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
th
on the function it performs (parity check, multiprocessor communication etc.)
th
the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
37
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